Q. New CPU whose instruction set includes the instruction set of its predecessor CPU is said to be ___________ with its predecessor.

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Q. What is the high speed memory between the main memory and the CPU called?

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Q. Cache Memory is implemented using the DRAM chips.

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Q. Whenever the data is found in the cache memory it is called as _________

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Q. LRU stands for ___________

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Q. When the data at a location in cache is different from the data located in the main memory , the cache is called _____________

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Q. Which of the following is not a write policy to avoid Cache Coherence?

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Q. Which of the following is an efficient method of cache updating?

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Q. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.

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Q. The number of sign bits in a 32-bit IEEE format is ____

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Q. The transfer between CPU and Cache is ______________

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Q. Computer has a built-in system clock that emits millions of regularly spaced electric pulses per _____ called clock cycles.

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Q. It takes one clock cycle to perform a basic operation.

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Q. The operation that does not involves clock cycles is _________

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Q. The number of clock cycles per second is referred as ________

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Q. CISC stands for ____________

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Q. Which of the following processor has a fixed length of instructions?

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Q. Processor which is complex and expensive to produce is ________

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Q. The architecture that uses a tighter coupling between the compiler and the processor is ____________

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Q. MAR stands for ___________

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