Q. Which of the following is not a write policy to avoid Cache Coherence?

View solution

Q. Which of the following is an efficient method of cache updating?

View solution

Q. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.

View solution

Q. The number of sign bits in a 32-bit IEEE format is ____

View solution

Q. The transfer between CPU and Cache is ______________

View solution

Q. Computer has a built-in system clock that emits millions of regularly spaced electric pulses per _____ called clock cycles.

View solution

Q. It takes one clock cycle to perform a basic operation.

View solution

Q. The operation that does not involves clock cycles is _________

View solution

Q. The number of clock cycles per second is referred as ________

View solution

Q. CISC stands for ____________

View solution

Q. Which of the following processor has a fixed length of instructions?

View solution

Q. Processor which is complex and expensive to produce is ________

View solution

Q. The architecture that uses a tighter coupling between the compiler and the processor is ____________

View solution

Q. MAR stands for ___________

View solution

Q. A circuitry that processes that responds to and processes the basic instructions that are required to drive a computer system is ________

View solution

Q. Any electronic holding place where data can be stored and retrieved later whenever required is ____________

View solution

Q. Cache memory is the onboard storage.

View solution

Q. Which of the following is the fastest means of memory access for CPU?

View solution

Q. The memory implemented using the semiconductor chips is _________

View solution

Q. Size of the ________ memory mainly depends on the size of the address bus.

View solution