Q. Dual inline memory modules (DIMMs) typically contains

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Q. If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be

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Q. Blocking optimization is used to improve temporal locality, for reduce

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Q. A direct-mapped cache has only 1 block/set and a

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Q. GDRAMs or GSDRAMs are known as Dynamic DRAMs, also called

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Q. 1000 MIPS processor for running programs successfully must have at-least

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Q. An architecture, allowing the Virtual machines for executing directly on the hardware , deserves the title

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Q. Advanced cache optimization has been divided into

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Q. The instruction miss which is serviced by the main memory, has total latency, approximately of

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Q. For estimating the accessing time and energy consumption of cache structure on CMOS microprocessors, the program used is

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Q. A reliable high-end processor: the Intel Core i7 has capability of generating two data memory references per core at every clock cycle; with 4 cores and a 3.2 GHz clock-rate, the data memory generated by i7 is,

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Q. Time for replacing the block from memory, is referred to as

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Q. For translating the virtual address, from the micro-processor to a physical-address for accessing memory, the memory used in this task is

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Q. The letters of SRAM, stands for

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Q. Virtual machines provide an abstraction that is used for running the complete software stack, this stated abstraction is known as

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Q. The time when a read instruction is requested and when the desired instruction arrives, is referred to as

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Q. A processor for going from a user mode to a supervisor mode, needs

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Q. A mapping that works well for spreading the block addresses sequentially all across the banks, are called

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Q. For completing the programmer's desire for unlimited quick memory, suggested economical solution was

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Q. Combination of instruction cycle and execution cycle is known as

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