Q. Asynchronous inputs, just like synchronous inputs, can be engineered to be ______________.

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Q. ___________ and Clear should not be 0 at the same time; otherwise, both the outputs will be 1, which is known as invalid state.

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Q. Which table indicates the input conditions of the flip-flops necessary to cause all possible next state transitions of a flip-flop?

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Q. When a circuit is self- correcting?

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Q. A PLA consists of two-level____________ circuits on a single chip.

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Q. In which of the following types of counters, the flip-flops do not change states at exactly the same time?

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Q. The number of states through which the counter goes is also known as ____________.

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Q. It contains an equal resistor or current source segment for each possible value of DAC output.

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Q. The total current can be converted into the corresponding voltage by using a/an _______________.

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Q. The number of resistors required for an N-bit DAC is 2N in the case of _____________.

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Q. The characteristics of a DAC, which are generally specified by the manufacturers

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Q. To start the conversion in successive approximation DAC the programmer sets the MSB to ___________ and all other bits to __________.

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Q. The major block(s) of the dual- slope ADC

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Q. A counter with 10 states

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Q. In asynchronous flip-flop, ______________ and clear pin shows negation.

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Q. It is a single input version of J-K flip-flop formed by tying both the inputs of J-K.

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Q. In flip-flop, the ___________ arrow shows positive transition on the clock.

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Q. Gated S-R latch is a combination of which latch and gate?

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Q. Which of the following is the advantage of PLD over ICs?

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Q. In a DAC, the possible number of digital input is __________.

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