Q. An implementation technique whereby multiple instructions are overlapped in execution, refers to

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Q. Grouping the 16 functional units together into four groups and supplying a set of buses, called

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Q. Example: the number of cars per hour and is determined by how often a completed car exits the assembly line, shows the

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Q. To improve the ability of the compiler to fill branch delay slots, most processors with conditional branches have introduced a

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Q. Pipelining that allows to achieve higher clock rates by decomposing the five-stage integer pipeline into eight stages, is refered as

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Q. When all instructions take the same number of cycles, which must also equal the number of pipeline stages the process is known as

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Q. Exceptions that are caused by some hardware event that is not under the control of the user program, refered as

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Q. Hazards in pipelines can make it necessary to

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Q. Indicating which of the four steps the instruction is in, is provided by

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Q. In pipelines with long-running operations, the possible caused issue is called

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Q. The effective pipeline speedup with branch penalties, assuming an ideal CPI of 1, is

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Q. For execution, branch instructions require 2 cycles, store instructions require 4 cycles, and all other instructions require

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Q. If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to

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Q. If the buffer is a queue with multiple instructions, it stalls when the queue

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Q. Instruction used in sequences to implement a more complex instruction set, is called a

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Q. A processor with separate decode and register fetch stages will probably have a

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Q. If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have a

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Q. Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is

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Q. The instruction in different stages of the pipeline do not interfere with one another, the separation is done by

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Q. MIPS pipeline with the appropriate registers, called pipeline registers or also known as

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