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Welcome to the Asynchronous Sequential Logic MCQs Page

Dive deep into the fascinating world of Asynchronous Sequential Logic with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Asynchronous Sequential Logic, a crucial aspect of Digital Logic Design. In this section, you will encounter a diverse range of MCQs that cover various aspects of Asynchronous Sequential Logic, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Digital Logic Design.

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Check out the MCQs below to embark on an enriching journey through Asynchronous Sequential Logic. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Digital Logic Design.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Asynchronous Sequential Logic. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Asynchronous Sequential Logic MCQs | Page 2 of 5

Explore more Topics under Digital Logic Design

Q11.
In primitive flow table for gated latch, each state has

a.

1 row

b.

2 rows

c.

3 rows

d.

4 rows

Discuss
Answer: (a).1 row
Q12.
In all the cases final stable state is

a.

changed

b.

same

c.

inverted

d.

undefined

Discuss
Answer: (b).same
Q13.
The complexity of asynchronous circuit is involved in timing problems of

a.

inputs

b.

outputs

c.

clock pulses

d.

feedback path

Discuss
Answer: (d).feedback path
Q14.
Instability condition can be determined from

a.

table

b.

map

c.

graph

d.

logic diagram

Discuss
Answer: (d).logic diagram
Q15.
Transition table consists of

a.

squares

b.

rectangles

c.

circles

d.

oval

Discuss
Answer: (a).squares
Q16.
A Condition occurs when an Asynchronous sequential circuit changes two or more binary states variables

a.

deadlock condition

b.

Running condition

c.

Race condition

d.

None

Discuss
Answer: (c).Race condition
Q17.
Time delay device is the memory element of

a.

Unclocked flip-flops

b.

clocked flip-flops

c.

synchronous circuits

d.

asynchronous circuits

Discuss
Answer: (d).asynchronous circuits
Q18.
The second step of making transition table is

a.

determining feedback loop

b.

designating output of loops

c.

deriving functions of Y

d.

plotting Y

Discuss
Answer: (b).designating output of loops
Q19.
Each logic gate gives delay of

a.

1 to 5 ns

b.

2 to 10 ns

c.

3 to 10 ns

d.

3 to 5 ns

Discuss
Answer: (b).2 to 10 ns
Q20.
The NAND latch works when both inputs are

a.

1

b.

0

c.

inverted

d.

don't cares

Discuss
Answer: (a).1
Page 2 of 5

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