Q. If two interrupts, of higher priority and lower priority occur simultaneously, then the service provided is for

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Q. For an interrupt to be guaranteed served it should have duration of

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Q. The service to an interrupt will be delayed if it appears during the execution of

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Q. The serial communication is

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Q. The serial communication is used for

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Q. The mcs 51 architecture supports

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Q. The number of bits transmitted or received per second is defined as

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Q. The task of converting the byte into serial form and transmitting it bit by bit along with start, stop and parity bits is carried out by

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Q. The transmission unit does not require assistance from processor if once a byte for transmission is written to

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Q. The common unit shared by the receiver unit and transmission unit of serial communication unit is

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Q. During serial reception, the buffer that receives serial bits and converts to a byte is

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Q. If SM0=1, SM1=0, then the transceiver selected is

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Q. If the microcontroller is expected to communicate in a multiprocessor system, then the required condition is

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Q. In mode 2, the baud rate depends only on

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Q. The mode that offers the most secured parity enabled data communication at lower baud rates is

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Q. The power control register is

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Q. The state of signals in idle mode is

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Q. To come out of idle mode, the external interrupt that is enabled is

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Q. The microcontroller enters into power down mode when

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Q. The clock signal is disabled to all parts of 8051 in

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