adplus-dvertising
frame-decoration

Question

The on-chip cache is controlled by

a.

Cache disable(CD)

b.

No write through(NW)

c.

Cache disable and No write through

d.

None of the mentioned

Answer: (c).Cache disable and No write through

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. The on-chip cache is controlled by

Similar Questions

Discover Related MCQs

Q. The on-chip cache is used for storing

Q. In Little Endian data format, the data is stored as

Q. The datatype that the 80486 does not support is

Q. The major limitation of 80386-387 system is

Q. The flag that is added to 80486 in additional to the flags similar to 80386 is

Q. The management of the virtual memory of the system and adequate protection to data or codes in the physical memory is provided by

Q. The unit that subjects the processor operation to boundary scan tests is

Q. Which of the following signal is handled by bus control and request sequencer?

Q. The first processor with an inbuilt floating point unit is

Q. The instruction that shifts 8 LSB bits of ECX into the MSB positions of EAX, one by one starting from LSB of ECX is

Q. The instruction that shifts the specified number of bits in the instruction, from the upper side of the source operand into the lower side of the destination operand is

Q. Which of the following is not a conditional set byte instruction?

Q. In case of BT instruction, if the bit position in the destination operand specified by the source operand, is ‘1’, then

Q. Which of the following is not a bit test instruction?

Q. If a ‘1’ is not encountered when an operand is scanned by BSR, then

Q. If a ‘1’ is encountered when an operand is scanned by BSF, then

Q. The BSR (bit scan reverse) instruction scans the operand in the order

Q. The BSF (bit scan forward) instruction scans the operand in the order

Q. Which of the following is not a newly added instruction of 80386, that are not present in 80286?

Q. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly connected to