Q. Assembler directives represent………………
1) Machine instructions to be included in the object program
2) The allocation of storage for constants or program variable

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Q. The bus system of a machine has the following propagation delay times 40 ns for the signals to propagate through the multiplexers, 90ns to perform the ADD operating in the ALU, 30ns delay in the destination decoder, and 20ns to store the data into the destination register. What is the minimum cycle time that can be used for the clock?

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Q. The sequence of events that happen during a typical fetch operation is ?

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Q. In a fully associative cache memory consisting of 256 cache lines of 16 bytes each, a tag field is of 14 bits. Determine the size of cache memory and main memory.

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Q. If doubling the cache line length reduces the miss rate to 3 percent, by how much it reduces the average memory access time?

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Q. Consider the following register – transfer language:

R₃ ← R₂+ M[R₁ + R₂]

Where R₁, R₂ are the CPU registers and M is a memory location in primary memory, which addressing mode is suitable for above register transfer language?

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Q. Booth′s algorithm is used in floating – point

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Q. A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of

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Q. What is the control unit’s function in the CPU?

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Q. In a two-level memory hierarchy, the access time of the memory is 12 nanoseconds and the access time of the main memory is 1.5 microseconds. The hit ratio is 0.98. What is the average access time of the two-level memory system?

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Q. Consider the following organization of main memory and cache memory.

Main memory: 64k ×16
Cache memory: 256 × 16

Memory is word addressable and block size of 8 words. Determine the size of tag field if the direct mapping is used for transforming data from main memory to cache memory.

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Q. A computer system has 4k – word cache organized in a block – set-associative manner, with 4 blocks per set, 64 words per block, memory is word addressable. The number of bits in the SET and WORD fields of the main memory address format is

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Q. Booth's coding in 8 bits for the decimal number −57 is:

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Q. What is the equivalent decimal representation for the following radix representation?

(34.44)₈

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Q. Find x & y values if the following equality is valid.

( X567 )₈ + ( 2YX5 )₈ = ( 71YX )₈

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Q. How many digits are required to represent 126 bit binary number in decimal?

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Q. Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011?

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Q. What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding?

(113.+−111.)+7.51
113.+(−111.+7.51)

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Q. (1217)₈ is equivalent to

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Q. P is a 16 – bit signed integer. The 2’s complement representation of P is (F87B)₁₆. The 2’s complement representation of 8 * p is

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