adplus-dvertising
frame-decoration

Question

After reset, CPU begins execution of instruction from memory address

a.

0101H

b.

8000H

c.

0000H

d.

FFFFH

Posted under Computer Architecture

Answer: (c).0000H

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. After reset, CPU begins execution of instruction from memory address

Similar Questions

Discover Related MCQs

Q. Synchronous means _______

Q. An effective solution to the power consumption problem lies in using _______ transistors to implement ICs.

Q. When CPU is executing a Program that is part of the Operating System, it is said to be in

Q. When a logic circuit diagram is given, you can analyse the circuit to obtain the _____________.

Q. IC chips based on packaging density are

Q. While designing a digital system, the main objectives are

Q. There are two types of parity

Q. This is the maximum time from the start of the valid address of the read cycle to the time when the valid data is available at the data output.

Q. In a sequential memory, the words are stored in and out in a sequence.

Q. A___________ is a semiconductor memory device used to store information, which is permanent in nature.

Q. Erasing EPROM programming is accomplished by using ultraviolet light that belongs to the UVC range and has a frequency of _____________________.

Q. The EPROM eraser will emit________________ light.

Q. ________________ organization is essentially an array of selectively open and closed unidirectional contacts.

Q. The EEPROM chip is physically similar to the chip.

Q. A memory stores data for processing and the instructions for _________.

Q. Number of stored bits per unit area, which determines overall storage capacity and memory cost per bit.

Q. The _______________ of the desired memory location is applied to the address input terminals.

Q. In a sequential memory, the words are stored in and read out in a_______________ .

Q. I/O function allows to exchange data directly between an

Q. Cache memory is intended to provide memory access