adplus-dvertising
frame-decoration

Question

Comparator_A+ is controlled by which of the following peripheral registers?

a.

CACTL1

b.

CACTL2

c.

Both of the mentioned

d.

None of the mentioned

Posted under Computer Architecture

Answer: (c).Both of the mentioned

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. Comparator_A+ is controlled by which of the following peripheral registers?

Similar Questions

Discover Related MCQs

Q. CAON bit is used to

Q. P2CA4-P2CA0 bits are used for

Q. CAREFx bits are used for

Q. Which of the following bits are not actually associated with the comparator module.

Q. Flag CAIFG is raised,

Q. Setting a bit in the Port Disable register CAPD causes the circuits for the usual digital input and output buffers to be disconnected from the appropriate pin.

Q. Which bit is used for exchanging the two inputs of the comparator and invert its output to compensate?

Q. Changes in Vcc changes the value of V+ ?

Q. The relaxation oscillator circuit helps in

Q. The successive approximation converters have resolution of

Q. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and set up the new voltage.

Q. The main operations that are basically performed in a SAR ADC are?

Q. Usually a capacitor is inserted between an analog input and the ground because

Q. ADC10 and ADC12 are

Q. ADC10 needs external capacitors on its voltage reference.

Q. ADC10CTL0 and ADC10CTL1 are registers

Q. While conversion is in progress, which of the flag is affected.

Q. ADC10SHTx bits allow_________cycles of the ADC10CLK.

Q. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?

Q. The basic idea behind the sigma delta converter is that