Q. Which architecture provides separate buses for program and data memory?

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Q. Which micro controller don’t match with its architecture below?

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Q. Harvard architecture allows:

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Q. Which out of the following supports Harvard architecture?

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Q. Why most of the DSPs use Harvard architecture?

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Q. Which of the following supports CISC as well as Harvard architecture?

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Q. Which of the two architecture saves memory?

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Q. Is the following instruction correct LDI R3,50?

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Q. Registers R0-R31 are used for what type of works?

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Q. Largest value that can be loaded in an 8 bit register is?

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Q. The total space for the data memory available in the AVR based micro controller is?

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Q. Which out of the following instructions don’t affect the flags of the status register?

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Q. What is the difference between the two given instructions?
LDI R16,0x34 and LDI R16,$34

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Q. Which out of the following is not a directive?

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Q. Is an assembly language a high level language?

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Q. A 14 bit program counter can execute a maximum of _________ memory locations?

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Q. When AVR wakes up, then the value of PC becomes?

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Q. Which of the following is correct about BRNE instruction in avr microcontrollers?

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Q. How many times is this loop going to get execute?

LDI R20, 10
now: LDI R21, 70
DEC R21
BRNE now
OUT PORTB, R20

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Q. Which of the below mentioned are not the conditional jumps?

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