Q. How many clocks are required for the first access in the burst interface?

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Q. In which of the following access, the address is supplied?

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Q. What type of timing is required for the burst interfaces?

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Q. How can gate delays be reduced?

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Q. In which memory does the burst interfaces act as a part of the cache?

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Q. Which of the following uses a wrap around burst interfacing?

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Q. Which of the following is a Motorola’s protocol product?

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Q. Which of the following uses a linear line fill interfacing?

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Q. Which of the following protocol matches the Intel 80486?

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Q. Which of the following protocol matches the MC68040?

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Q. The modified bit is also known as

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Q. Which of the following have a 8 KB page?

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Q. Which of the following address is seen by the memory unit?

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Q. Which of the following modes offers segmentation in the memory?

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Q. Which of the following is necessary in the address translation in the protected mode?

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Q. What does “G” in the descriptor entry describes?

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Q. How many types of tables are used by the processor in the protected mode?

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Q. What does table indicator indicates when it is set to one?

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Q. What does GDTR stand for?

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Q. What does PMMU stands for?

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