Q. Which of the following address is seen by the memory unit?

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Q. Which of the following modes offers segmentation in the memory?

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Q. Which of the following is necessary in the address translation in the protected mode?

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Q. What does “G” in the descriptor entry describes?

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Q. How many types of tables are used by the processor in the protected mode?

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Q. What does table indicator indicates when it is set to one?

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Q. What does GDTR stand for?

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Q. What does PMMU stands for?

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Q. Which of the following support virtual memory?

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Q. What does DPL in the descriptor describes?

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Q. What does “S” bit describes in a descriptor?

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Q. How many regions are created by the memory range in the ARM architecture?

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Q. How many bit does the memory region in the ARM memory protection unit have?

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Q. Which of the following uses a priority level for permitting data?

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Q. What type of bit in the ARM memory mimics to that of the protection unit of ARM management unit?

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Q. Which of the following bits are used to control the cache behaviour?

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Q. Which of the following unit provides security to the processor?

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Q. Which of the following includes a tripped down memory management unit?

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Q. Which of the following can reduce the chip size?

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Q. How does the memory management unit provide the protection?

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