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Question

Which of the following is not a stage of pipeline of a RISC processor?

a.

read registers and decode the instructions

b.

fetch instructions from registers

c.

write result into a register

d.

access an operand in data memory

Posted under RISC Architecture Microprocessor

Answer: (b).fetch instructions from registers

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Q. Which of the following is not a stage of pipeline of a RISC processor?
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