Q. The number of instructions that can be executed per clock cycle by the ALU or AGU is

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Q. The paging mechanism of IA-32 architecture has an extension as

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Q. The linear address space is mapped into the processors physical address space either directly or through paging by

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Q. The features of thread in threading process is

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Q. The process in which multiple threads correspond to the tracking of each individual object is known as

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Q. The thread level parallelism is a process of

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Q. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?

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Q. Who introduced Pentium family?

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Q. In which year, Pentium pro processor introduced?

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Q. _______ has been enhanced to provide higher performance for multimedia & communication applications.

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Q. ________ is used in desktop and laptop personal computers.

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Q. Pentium II processor was introduced in the year _______.

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Q. Pentium II xeon processor offers _______ performance than the std Pentium II processor.

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Q. Dual independent bus architecture was first introduced in the ________________.

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Q. How many buses provided in Pentium II processor?

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Q. Pentium III processor was introduced in _______.

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Q. The processor 80386/80486 and the Pentium processor uses _____ bits address bus.

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Q. The Pentium microprocessor has______execution units.

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Q. The memory data bus width in Pentium is

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Q. If the logical processors want to execute complex IA-32 instructions simultaneously then the number of microcode instruction pointers required is

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