Q. The unit that decodes the instructions concurrently and translate them into micro-operations is

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Q. In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to

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Q. The unit that does not store the instructions, but the decoded stream of instructions is

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Q. Trace cache can store the micro-ops upto a range of

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Q. The unit that predicts the locations from where the next instruction bytes are fetched is

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Q. If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to

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Q. After the micro-ops are issued by the microcode ROM, the control goes to

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Q. The units that are primarily used to resolve indirect mode of memory addressing is called

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Q. The AGUs work at a speed of

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Q. Pentium 4 consists of

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Q. The number of instructions that can be executed per clock cycle by the ALU or AGU is

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Q. The paging mechanism of IA-32 architecture has an extension as

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Q. The linear address space is mapped into the processors physical address space either directly or through paging by

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Q. The features of thread in threading process is

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Q. The process in which multiple threads correspond to the tracking of each individual object is known as

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Q. The thread level parallelism is a process of

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Q. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?

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Q. Who introduced Pentium family?

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Q. In which year, Pentium pro processor introduced?

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Q. _______ has been enhanced to provide higher performance for multimedia & communication applications.

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