Q. A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as

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Q. In a microprocessor system, suppose. TRAP, HOLD, RESET Pin got activated at the same time, while the processor was executing some instructions, then it will first respond to

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Q. When CPU is not fully loaded, which of the following method of data transfer is preferred

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Q. In microprocessor, the SS is called as ________.

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Q. The index register are used to hold _______.

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Q. The BIU contains FIFO register of size __________ bytes.

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Q. The BIU pre-fetches the instruction from memory and store them in ________.

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Q. The CS register stores instruction _____________ in code segment.

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Q. The microprocessor determines whether the specified condition exists or not by testing the ______.

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Q. The _________ translates a byte from one code to another code.

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Q. The BIU contains FIFO register of size 6 bytes called _____.

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Q. The pin of minimum mode AD0-AD15 has ____________ address.

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Q. The pin of minimum mode AD0- AD15 has _________ data bus.

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Q. Bits in IRR interrupt are ______.

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Q. __________ generate interrupt signal to microprocessor and receive acknowledge.

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Q. The _______ pin is used to select direct command word.

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Q. BURST refresh in DRAM is also called as ___________.

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Q. For the most Static RAM the maximum access time is about ____________.

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Q. Which of the following statements on DRAM are correct?

- Page mode read operation is faster than RAS read.
- RAS input remains active during column address strobe.
- The row and column addresses are strobed into the internal buffers using RAS and CAS inputs respectively

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Q. Accumulator based microprocessor example are:

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