Q. In instruction execution of pipelined processor the WB stage is the

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Q. The given set of instructions add $s0, $t0, $t1; sub $t2, $s0, $t3; shows the

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Q. Branch, MemWrite and MemRead are control lines set of

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Q. Make a decision based on the results of above instruction while its being executed, is referred to as

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Q. Delay in finding the proper instruction to fetch is known as control hazard, also referred to as

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Q. To discard instructions in the pipeline is referred to as

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Q. Predicting branches at runtime by using run-time information, is known as

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Q. The instruction being read from memory using the address placed in the PC and then is placed in the IF/ID pipeline register in,

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Q. Pipeline stalling concept is often given the name of

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Q. An instruction that does no operation for changing state is known as

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Q. When multiple-instructions are overlapped during execution of the program, then function performed is called

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Q. The term specifying both the programs and the relative frequencies is known as

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Q. Register $2 written by subtraction can be written in the instruction

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Q. The hazards in the pipelined stages are of

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Q. The execution cycle with a branch, delay of one is

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Q. A floating-point divider, a floating-point multiplier, and a floating-point adder, are the parts of a

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Q. The time required between moving an instruction one step down the pipeline is a

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Q. Pipeline interlock introduces a stall or bubble, just as in the

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Q. MIPS pipeline with the appropriate registers, called pipeline registers or also known as

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Q. The instruction in different stages of the pipeline do not interfere with one another, the separation is done by

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