adplus-dvertising
frame-decoration

Question

Desirable characteristic(s) of a memory system is(are)

a.

Speed and reliability

b.

Low power consumption

c.

Durability and compactness

d.

All of these

Posted under Computer Architecture

Answer: (d).All of these

Engage with the Community - Add Your Comment

Confused About the Answer? Ask for Details Here.

Know the Explanation? Add it Here.

Q. Desirable characteristic(s) of a memory system is(are)

Similar Questions

Discover Related MCQs

Q. The minimum time delay required between initiation of two successive memory operations is called

Q. For a memory system, the cycle time is

Q. Generally , the refreshing rate of dynamic RAMs is approximately once in

Q. In comparison with static RAM memory, the dynamic RAM memory has

Q. Disadvantage of dynamic RAM over static RAM is

Q. Memory consisting of electronic circuits attached into silicon chip is known as

Q. Which of the following is the internal memory of the system (computer) ?

Q. The idea of cache memory is based on

Q. What is the correct sequence of time delays that happen during a data transfer from a disk to memory?

Q. An 24 bit address generates an address space of ______ locations .

Q. If a system is 64 bit machine , then the length of each word will be ____ .

Q. The type of memory assignment used in Intel processors is _____ .

Q. When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____ .

Q. To get the physical address from the logical address generated by CPU we use ____ .

Q. _____ method is used to map logical addresses of variable length onto physical memory.

Q. During transfer of data between the processor and memory we use ______ .

Q. Physical memory is divided into sets of finite size called as ______ .

Q. Which is true for a typical RISC architecture?

Q. SIMD represents an organization that ______________.

Q. Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?