Q. How does the Hardware trigger an interrupt ?

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Q. Which operation is performed by an interrupt handler ?

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Q. Why is the Software interrupt required by the processor?

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Q. Match the following list1 with list2:
a. DMA I/O -------------------------------------- 1. High speed RAM
b. Cache ---------------------------------------- 2. Disk
c. Interrupt I/O --------------------------------- 3. Printer
d. Condition code register ------------------- 4. ALU

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Q. Which of the following is an example of Spooled Device?

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Q. The following is not a layer of IO management module

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Q. If one or more devices use a common set of wires to communicate with the computer system, the connection is called ______

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Q. A ____ a set of wires and a rigidly defined protocol that specifies a set of messages that can be sent on the wires.

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Q. When device A has a cable that plugs into device B, and device B has a cable that plugs into device C and device C plugs into a port on the computer, this arrangement is called a _________

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Q. The _________ present a uniform device-access interface to the I/O subsystem, much as system calls provide a standard interface between the application and the operating system.

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Q. A ________ is a collection of electronics that can operate a port, a bus, or a device.

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Q. An I/O port typically consists of four registers status, control, ________ and ________ registers.

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Q. The ______ register is read by the host to get input.

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Q. The ______ register is written by the host to send output.

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Q. The hardware mechanism that allows a device to notify the CPU is called _______

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Q. The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.

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Q. The _________ determines the cause of the interrupt, performs the necessary processing and executes a return from the interrupt instruction to return the CPU to the execution state prior to the interrupt.

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Q. In general the two interrupt request lines are :

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Q. The _________ are reserved for events such as unrecoverable memory errors.

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Q. The ________ can be turned off by the CPU before the execution of critical instruction sequences that must not be interrupted.

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