Q. The percentage of times a page number is found in the TLB is known as :

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Q. Memory protection in a paged environment is accomplished by :

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Q. When the valid – invalid bit is set to valid, it means that the associated page :

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Q. Illegal addresses are trapped using the _____ bit.

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Q. When there is a large logical address space, the best way of paging would be :

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Q. In a paged memory, the page hit ratio is 0.35. The required to access a page in secondary memory is equal to 100 ns. The time required to access a page in primary memory is 10 ns. The average time required to access a page is :

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Q. To obtain better memory utilization, dynamic loading is used. With dynamic loading, a routine is not loaded until it is called. For implementing dynamic loading,

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Q. In paged memory systems, if the page size is increased, then the internal fragmentation generally :

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Q. In segmentation, each address is specified by :

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Q. In paging the user provides only ________ which is partitioned by the hardware into ________ and ______

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Q. Each entry in a segment table has a :

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Q. The segment base contains the :

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Q. The segment limit contains the :

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Q. The offset ‘d’ of the logical address must be :

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Q. If the offset is legal :

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Q. When the entries in the segment tables of two different processes point to the same physical location :

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Q. The protection bit is 0/1 based on :

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Q. If there are 32 segments, each of size 1Kb, then the logical address should have :

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Q. Consider a computer with 8 Mbytes of main memory and a 128 K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block ?

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Q. A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because :

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