Q. A half-adder is also known as :

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Q. When an inverter is placed between both inputs of an S-R flip flop, the resulting flip flop is:

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Q. The Register or main memory location which contains the effective address of the operand is known as:

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Q. Identify the logic function performed by the circuit shown

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Q. When a tri-state logic device is in the third state, then:

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Q. An example of a connective which is not associative is:

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Q. Essential hazards may occur in:

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Q. The characteristic equation of a T flip-flop is:

(A) Qn+1=TQ’n + T’ Qn              
(B) Qn+1=T+Qn
(C) Qn+1=TQn                   
(D) Qn+1= T’Q’n

The symbols used have the usual meaning.

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Q. The maximum size of main memory of a computer is determined by:

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Q. In computer terminology, POST stands for:

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Q. IC 74 LS 138 is a:

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Q. A hardware interface that allows for the connection of several peripheral devices to a single PCI board

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Q. Simplified form of the Boolean expression Y=A’BC’D’+ABC’D’+A’BCD’+ABCD’ is:

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Q. Which of the following statements are true?

(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
(ii) Boolean expressions and logic networks correspond to labelled acyclic diagraphs.
(iii) No two Boolean algebras with n atoms are isomorphic.
(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.

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Q. In computers, subtraction is generally carried out by

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Q. Consider the following boolean equations:

(i) wx + w(x+y) + x(x+y) = x + wy
(ii) (wx’(y+xz’) + w’x’)y = x’y

What can you say about the above equations?

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Q. Consider the following statements:

(i) Auto increment addressing mode is useful in creating self-relocating code.
(ii) If auto increment addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculation.
(iii) In auto incrementing addressing mode, the amount of increment depends on the size of the data item accessed.
Which of the above statements is/are true?

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Q. A computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in the operation code, the register code part and the address part?

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Q. Consider the following x86 – assembly language instructions:

MOV AL, 153
NEG AL

The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag (CF) and Sign Flag (SF) after the execution of above instructions, are

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Q. CMOS is a Computer Chip on the motherboard, which is:

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