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Question

With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for

a.

0 clock cycle

b.

1 clock cycle

c.

2 clock cycles

d.

3 clock cycles

Posted under Microprocessor

Answer: (c).2 clock cycles

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Q. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for

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