Q. The watchdog counts up and resets the MSP430 when it reaches the limit?

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Q. Which of the following is correct about WDTCTL?

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Q. WDTNMI is found in the

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Q. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?

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Q. WDTISx bits control the

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Q. The process of setting the WDTCNTCL bit in WDTCTL is through

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Q. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG (WDTCNTCL|WDTSSEL)**

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Q. Is this instruction correct?
WDTCTL_bit.WDTCNTCL = 1;

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Q. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as

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Q. WDTIFG flag gets cleared if

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Q. Which of the following is true about the BTFRFQx bits of the BTCTL register?

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Q. Timer1 is responsible for

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Q. For fACLK = 32 KHz, what would be the desirable range of flcd?

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Q. Normally BTCNT1 only function is to provide a prescalar for the BNTCNT2?

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Q. BTCNT2 provides 2 output signals?

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Q. RTCSEC, RTCMIN, RTCDOW etc. are the bytes of a set of registers that are used to store

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Q. The RTC module is configured in the calendar mode if

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Q. THE RTC module makes use of the Basic Timer1 because

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Q. IF RTCIE interrupt is generated then

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Q. What does the RTCTEVx bits do?

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