Q. When the set of input data to an even parity generator is 0111, the output will be

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Q. How many flip-flops are required to construct mod 30 counter

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Q. The number of control lines for 16 to 1 multiplexer is

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Q. The number of control lines for 32 to 1 multiplexer is

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Q. The logic 0 level of a CMOS logic device is approximately

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Q. How many select lines will a 32:1 multiplexer will have

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Q. Which of following consume minimum power?

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Q. ABCD - seven segment decoder / driver in connected to an LED display. Which segments are illuminated for the input code DCBA = 0001.

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Q. How many flip-flops are required to produce a divide-by-32 device?

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Q. A demultiplexer can be used as

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Q. 'n' Flip flops will divide the clock frequency by a factor of

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Q. If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than the output of the cascaded arrangement shall be of

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Q. Logic gates with a set of input and outputs is arrangement of

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Q. A flip-flop is a binary cell capable of storing information of

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Q. A device/circuit that goes through a predefined sequence of states upon the application of input pulses is called

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Q. A combinational logic circuit which sends data coming from a single source to two or more separate destinations is

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Q. Advantage of synchronous sequential circuits over asynchronous ones is

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Q. A basic AND gate consists of ______________inputs and an output.

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Q. In the AND gate, the output is ‘High’ or gate is ‘On’ only if both the inputs are ______________.

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Q. It is a simple combinational digital circuit built from logic gates

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