Q. How many classifications of DMA controllers are made based on the addressing capability?

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Q. How many address register are there for the 1D type DMA controller?

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Q. Which of the following of a generic DMA controller contain a base address register and an auto-incrementing counter?

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Q. Which of the following is used to transfer the data from the DMA controller to the destination?

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Q. Which of the following is used to request the bus from the main CPU?

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Q. Which signal can identify the error?

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Q. Which signal allows the DMA controller to select the peripheral?

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Q. Which of the following is also known as implicit address?

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Q. Which address mode uses two addresses and two accesses to transfer the data between the peripheral and the memory?

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Q. Which of the following address mode uses a buffer to hold data temporarily?

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Q. Which of the following model can implement circular buffer?

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Q. Which of the following uses an address and a counter to define the sequence of addresses?

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Q. Which of the following is used to calculate an offset to base address?

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Q. Which can provide an address stride?

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Q. How is the count register can be splitted?

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Q. Which of the following has the ability to change the stride automatically?

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Q. Which is used to prioritise multiple request?

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Q. Which of the following DMA is used in the IBM PC?

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Q. Which signal is sampled at regular intervals for the purpose of ADC?

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Q. Which factor depends the quantisation error?

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