Q. ______ bus structure is usually used to connect I/O devices .

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Q. The I/O interface required to connect the I/O device to the bus consists of ______

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Q. To reduce the memory access time we generally make use of ______ .

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Q. ______ is generally used to increase the apparent size of physical memory .

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Q. MFC stands for

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Q. The time delay between two successive initiation of memory operation _______ .

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Q. The decoded instruction is stored in ______ .

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Q. The instruction -> Add LOCA,R0 does,

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Q. Which registers can interact with the secondary storage ?

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Q. During the execution of a program which gets initialized first ?

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Q. Which of the register/s of the processor is/are connected to Memory Bus ?

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Q. ISP stands for,

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Q. The internal Components of the processor are connected by _______ .

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Q. ______ is used to choose between increment the PC or performing ALU operations .

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Q. The registers, ALU and the interconnection between them are collectively called as _____ .

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Q. _______ is used to store data in registers .

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Q. During the execution of the instructions, a copy of the instructions is placed in the ______

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Q. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster ?

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Q. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ .

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Q. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?

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