Q. In this type of counter, the output of the last stage is connected to the D input of the first stage.

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Q. In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state.

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Q. In this type of register, data can be shifted in either right or left direction by using control signal.

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Q. This type of register accepts inputs data simultaneously and output is also coming out parallel

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Q. This type of register accepts inputs data serially

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Q. There are ___________ basic types of shift registers.

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Q. A register used to provide data movements

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Q. It does not have any external gate.

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Q. An n-bit register has a group of n flip-flops and some

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Q. In a DAC, the possible number of digital input is __________.

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Q. Which of the following is the advantage of PLD over ICs?

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Q. Gated S-R latch is a combination of which latch and gate?

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Q. In flip-flop, the ___________ arrow shows positive transition on the clock.

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Q. It is a single input version of J-K flip-flop formed by tying both the inputs of J-K.

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Q. In asynchronous flip-flop, ______________ and clear pin shows negation.

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Q. A counter with 10 states

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Q. The major block(s) of the dual- slope ADC

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Q. To start the conversion in successive approximation DAC the programmer sets the MSB to ___________ and all other bits to __________.

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Q. The characteristics of a DAC, which are generally specified by the manufacturers

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Q. The number of resistors required for an N-bit DAC is 2N in the case of _____________.

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