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Question

Which of the following condition is true for determining overflow condition in 2’s complement?

a.

When adding two positive numbers gives a negative result or when two negatives give a positive result.

b.

If sign bit (MSB) of result and sign bit of two operands are of different signs.

c.

The ‘1’ in the MSB position indicates a negative number after adding two positive numbers.

d.

All of the above

Posted under Computer Architecture

Answer: (d).All of the above

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Q. Which of the following condition is true for determining overflow condition in 2’s complement?
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