Q. What are the essential prime implicants of the following Boolean functions?

F (a, b, c) = a'c + ac' + b'c

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Q. A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

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Q. Consider a Boolean function f(w,x,y,z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i₁=⟨w₁,x₁,y₁,z₁⟩ and i₂=⟨w₂,x₂,y₂,z₂⟩ , we would like the function to remain true as the input changes from i₁ to i₂ (i₁ and i₂ differ in exactly one bit position) without becoming false momentarily. Let f(w,x,y,z)=∑(5,7,11,12,13,15) . Which of the following cube covers of f will ensure that the required property is satisfied?

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Q. Define the connective * for the Boolean variable X and Y as :

X * Y = XY + X'Y'.

Let Z = X * Z.Consider the following expression P, Q and R.
P : X = Y * Z
q : Y = X * Z
R : X * Y * Z = 1

Which of the following is true?

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Q. If P,Q,R are boolean variables, then (P+Q’)(PQ’+PR)(P’R’+Q’) simplifies to

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Q. In an SR latch made by cross coupling two NAND gates, If both S and R inputs are set to 0, then it will result in

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Q. The purpose of latch feedback is?

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Q. The minimum number of D flip – flops needed to design a mod – 258 counter is

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Q. A 10 – bit Asynchronous counter is having initial value 0 1 0 0 0 1 1 1 1 1. How many flip flops are complemented at next clock?

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Q. A sequential circuit is having one input and 2 states; The clock is initially in state A. It remains in the same state as long as (x=0) (i.e., input =0). If the input is 1, it switches to the state B and remains there as long as input is 0. On receiving 1 it switches back to state A. If it is realized with D – FF. what is the expression for D FF?

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Q. How many 3 – to – 8 line decoders with an enable input are needed to construct a 6 – to – 64 line decoder without using any other logic gates?

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Q. Let the 3 variable function f (a, b, c) = Σ (0, 1, 4, 5,7) is realized with 4x1 mux. The select line S₁ & S₀ are connected with A, B. What will be the connections for data inputs?

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Q. Consider a 3-variable function; f(A, B,C) = S (0, 1, 2, 4). It is realized with a 4x1 multiplexer; select lines S₁ S₀ are taken as B, C. Later it was found that select lines have to be interchanged w.r.t the data line in both terminations, Identify the correct statements.

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Q. Consider a binary channel which has 1 – input and 1 – output initially the input is reproduced at output until two consecutive zero’s are received from then onwards output is the bit – wise complement of input complement continuous until two consecutive 1’s are received at input, from then onwards it repeats the behaviour. What will be the minimum number of states in this binary channel.

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Q. A sequence machine is supposed to receive block of 0’s & 1’s the correct operation required 1’s, number of 1’s in 1st block must be odd and number of 0’s in 0’s block must be even. Any violation indicated by machine outputs 1 against 1st bit of opposite block. What will be minimum number of states in the sequence machine?

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