Q. A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

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Q. Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

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Q. A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.

zk - nk = 2. In this case, the output at the k-th and
all subsequent clock ticks is 10.
nk - zk = 2. In this case, the output at the k-th and
all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?

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Q. Let f(A, B) = A' + B. Simplified expression for function f(f(x + y, y)z) is :

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Q. Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:

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Q. A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

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Q. Consider the operations f(X, Y, Z) = X'YZ + XY' + Y'Z'  and  g(X′, Y, Z) = X′YZ + X′YZ′ + XY. Which one of the following is correct?

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Q. The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________.

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Q. The number of min-terms after minimizing the following Boolean expression is _________.

[D′ + AB′ + A′C + AC′D + A′C′D]′

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Q. A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is

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Q. The total number of prime implicants of the function f(w, x, y, z) = Σ(0, 2, 4, 5, 6, 10) is ________.

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Q. Given the function F = P′ + QR, where F is a function in three Boolean variables P, Q and R and P′ = !P, consider the following statements.

S1: F = Σ (4, 5, 6)
S2: F = Σ (0, 1, 2, 3, 7)
S3: F = Π (4, 5, 6)
S4: F = Π (0, 1, 2, 3, 7)

Which of the following is true?

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Q. What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?

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Q. Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow? (i) 1100 + 1100 (ii) 0011 + 0111 (iii) 1111 + 0111

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Q. The number (123456)8 is equivalent to

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Q. The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to

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Q. Which of the following expressions is equivalent to (A⊕B)⊕C

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Q. Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as

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Q. How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

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Q. We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is

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