Q. During the execution of DADD R1,R2,R3; DSUB R4,R1,R5; AND R6,R1,R7; OR R8,R1,R9; XOR R10,R1,R11, DSUB instruction reads the value during its ID stage. This problem is called a

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Q. Exceptions that occur within instructions are usually

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Q. When the compiler attempts to schedule instructions to avoid the hazard; this approach is called

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Q. Decoding is done in parallel with reading registers, which is possiblebecause the register specifiers are at a fixed location, the stated technique is called a

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Q. Pipelining increases the CPU instruction

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Q. Control hazards can cause a greater performance loss for MIPS pipeline than do

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Q. The sum of the contents of the base register and the sign-extended offset is used as a memory address, the sum is known as

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Q. The presence of antidependences and output dependences, leads to

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Q. The process of letting an instruction move from the instruction decode stage into the execution stage of this pipeline is usually called

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Q. To solve the problems with a simple hardware technique called forwarding, also known as

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Q. Every MIPS instruction can be implemented in at most

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Q. Code containing redundant loads, stores, and other operations that might be eliminated by an optimizer, is a

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Q. Delays arising from the use of a load result 1 or 2 cycles after the loads, refers as

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Q. Situations that prevent the next instruction in the instruction stream, from executing during its designated clock cycle are known as

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Q. The simplest dynamic branch-prediction scheme is a

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Q. When an instruction is guaranteed to complete, it is called

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Q. An implementation technique whereby multiple instructions are overlapped in execution, refers to

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Q. Grouping the 16 functional units together into four groups and supplying a set of buses, called

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Q. Example: the number of cars per hour and is determined by how often a completed car exits the assembly line, shows the

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Q. To improve the ability of the compiler to fill branch delay slots, most processors with conditional branches have introduced a

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